analog devices fax-on-demand hotline - page 2 rill analog w devices i features complete with high accuracy sample/hold and aid converter differential nonlinearity: :: 0.002% fsr max idas1153) nonlinearity: das1152: ::0.005% fsr max das1153: ::0.003% fsr max low differential nonlinearity t.c.: ::2ppmrc max high throughput rate: 25khz mln (das1152) high feedthrough rejection: -96db byte-selectable tri-state buffered outputs internal gain be offset potentiometers improved second source to aid/aim 824 and aid/aim 825 modules applications process control data acquisition automated test equipment seismic data acquisition nuclear instrumentation medical instrumentation robotics general description the das1152/das1153 are 14-/15-bit sampling analog-to-digital converters having a maximum throughput rate of 25khz/20khz. they provide high accuracy, high stability, and functional completeness all in a 2" x 4" x 0.44" metal case. guaranteed high accuracy system performance such as nonlinearity of ::0.005% fsr (das1l52)/:to.003% fsr (das1l53) and differentia! nonlinearity of :to.003% fsr (das1l52)/:to.oo2% fsr (das1l53) are provided. guaranteed stability such as differential nonlinearity t.c. of :t 2ppml"c (das 1153) maximum, zero t.c. of :t80f.l.vi"c maximum, gain t. c. of :t8ppmt'c maximwn and power supply sensitivity of :to.ool% fsr/% vs are also provided by the das1l52/daslls3. rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. 14-bit & 15-bit sampling analog-to-digital converters das1152/das1153 i functional block diagram ref out ~i f,."suo analoo { : input . tri. state suffers ms. ..aa lit 2 bit, 81f. ilf . elf . 81f 1 la e""sle sih output '5im input frl. statf ",,"er' bit . alt' bit ,. bit 11 bl1 11 bit n alt ,. '"58 for das,,521 bit ,. (lss for oas"o31 +w +15v ian"'-do .. digital qnos __ar..!.!:~~c:!"~~"!!.a~l!.! digital gnd -isv ,.". ut ,s the analog $!ghal ihput if th. ",""hal " analog devices fax-on-demand hotline - page 3 das1152/d~s1153 -specifications (typical@ +25oc unless otherwise specified.) dasl152 das1l53 outline dimensions 14 bits l5bi", dimensions shown in inches and (mm). model resolution dynamic performance througbput !tate conversion time 5th acquisition time sir apeffu", delay sth apenure uncertainty feedtbrough rejeclion i droop rate dielectric absorption error accuracy integral nonlinearity2 differential nonjinearity no missingcodes :t30'noise(s/h plus aid) :t30'noise(aid) stability differential nonlinearity t.c. gaint.c. arot.c. power supply sensitivity analog input voltage range bipolar unipolar adcinputlmpedanceoto +5v oto+iov,:dv :tiov sir input impedance digital inputs convert command' sth control low enable, high enable digital outputs paralld data outputs unipollr bipolar output drive status output drive internal reference voltage external load current (rated performance) temperature stability power requirements rated voltages opentingvoltages' supply current drain:!: 15v +sv temperature range specified operaling storage relative humidity shielding size 25khzmin 35j.1.s max 4flsmax sons ins -%db o.os...v/ (o.ij..vlj.l.smax) !; 0.005% oflnput voltage change ;i: 0.005% fsr'max :!:0.003%fsr'max guaranteed 75..vrms 50.. v rms :!:2ppmrcmax :!; 8ppml"c max :!: 30flvrctyp, .!: go...vr'cmax :to.ool%fsr'io/. v, :t5v, :!:iov oto+5v,oto+iov 2.51d1 5ko 10.oko loomnispf ittl load, positive pulse negative edge triggered hold ~ logico sample - logic i enable - logko binary offset binary, 2'. compjemem 2ttlload. logie "i" during conversion 2ttlloads +iov,:1:0.3% 2ma max :!: sppmrcli1u :t15v(:t:3%), + 5v (:!: 5%) . :t12vto+i7v,+4.75vto+s.25v . :t37ma soma 010 + 7o"c - 25"cto + 8s'c -25"clo +85"c . mccts mil.std-202e, method 103b . electrostatic (rfi) 6 sides, . electromagnctic (emi) 5 sides 2" x 4" x 0.44' mctalpackage 20khzmin 44j.1.smax s max . :to.003% fsrjrnax :!:0.002% fsrjmax . . . notes 'spcw .u...,...;... c{ sit{ and aid ...ii...,;" enon. 'fsr fud seal< rana<. 'whe. e.lin:d...d lhe sih e roile""iiia!> ,..."htt. ihe p.""..idlh must be to". enou.. fur "'" sm amplif.., '" ""qui... ihe i.p., 1 10 lbe requi,.,j ""'.my .", (mu. nasiis2)!5... (mu. nhsll~3). if ih. no ",.vmer i. only us?!, the eon , command po'" ..;dlh ohouid be 1_. <- fi8>jre z}. 'if only ,be aoc """'" is witd. ii>< ojictowc """"' iiupj'i>' vo!iqe an be inod "' '" i2v ,. '" ttv. bul ;f w sit{ sect " ""!oirc.11 .-- ,..-.. top v- 'f"" moo" "" - ." " "so" ufoii moon dab"". "".. "'b' easo is not hoilmet1cau.v so , ~ 1--0_1 ("""'." assembly instructions caution: this module is not an embedded assembly and is not hermetically sealed. do not subject to a solvent or water-wash process that would allow direct contact with free liquids or vapors. entrapment of contaminants may occur, causing performance degradation and permanent damage. install after any clean/wash process and then only spot clean by hand. ~-- rev. a -2- "';to< ............ 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analog devices fax-on-demand hotline - page ~ applying the das1152/das1153 operation the dasli52/das 1153 are functionally complete data acquisition subsystems being fully characterized as such. all the necessary data acquisition and microprocessor interface elements are provided internal to these devices. accuracy and performance criteria are tested and specified for the entire system. thus, design time and associated high accuracy problems are minimized because layout and component optimi7a1tion have already becn performed. for operation, the only connections necessary to the dasl1521 das1l53 are the :t: 15v and + 5v power supplies, analog input signal, trigger pulse, and the hi.enable/lo-enable tri- state controls. analog input and digital output programming are user selectable via external jumper connections. analog input section the analog input can be applied to just the aid converter or to the internal sample/hold amplifier ahead of the aid converter. when using just the aid converter, apply the analog input per the voltage range pin programming shown in table 1. when using the samplejhold amplifier in conjunction with aid con- verter, apply tbe analog input to the sir input terminal and connect the s/h output terminal to tbe appropriate aid converter analog input. table i. analog input pin programming 'noconncctiod errors due to source loading arc eliminated since the sample/hold amplifier is a high-impedance unity-gain amplifier. high feed through rejection is provided for either single-channel or multichannel applications. feedthrough rejection can be optimized, in multichannel applications, by changing channels at the rising or falling edge of the s/h control pulse. ref out gain adjust r- -----. i i i connect i for i bipolar i operation i i l- , ana in 1 ana in z ana1.og input range selection ana in 3 sih output sih input 51h control figure 2. analog input block diagram rev. a timing diagram the timing diagram for the daslls2/das1l53 is illustrated in figure 3. this figure also includes the samplc/hold amplifier acquisition time. if the sample/hold amplifier is required, the trigger input and s/h control terminal can be tied together providing only one conversion control signal. when the trigger pulse goes high, it places the sample/hold amplifier in the sample mode allowing it to acquire the present input signal. the trigger pulse must remain high for a minimum of 4fls (dasl152)/5fls (das 1153) to insure accuracy is attained. if the sample/hold amplifier is not used, the trigger pulse needs to be onjy loons (min) in length to satisfy the aid converter trigger requirements. at the falling edge of the trigger pulse, the sample/hold amplifier is placed in the hold mode, the aid conversion begins, and all internal logic is reset. once the conversion process is initiated, it cannot bc retriggered until after the end of conversion. with this negative edge of the trigger pulse the msb is set low with the remaining digital outputs set to logic high state, and the status line is set high and remains high through the full conversion cycle. during conversion each bit, starting with the msb, is sequentially switched low at the rising edge of the internal clock. the dac output is then compared to the analog input and the bit decision is made. each comparison lasts one clock cycle with the complete l4-/15-bit conversion taking 35flsi 44fls maximum for the das1l52/dasl153 respectively. at this time, the status line goes low signifying that the conversion is complete. for microprocessor bus applications, the digital output can now be applied to the data bus by enabling the tri- state buffers. for maximum data throughput, the digital output data should be read while the samplc/hold amplifier is acquiring the new analog input signal. trigger! r-1 sih control.j t . . inpljt +fs-r-+ signal -~ j=:- i , +f5 ~ slh output 0 - -: -fs -, """"" ~ n n n ci.ock t-j l..i l..i l..- eoc 35 i\iiax ( ~~ 44,.. i\iiax (0~~~:~1--t.- msb ==~lj ss ~ ' 81t 2 =~~~s - ' iiit3:==~~s -, 'i i t i i i i i i i i lilt 14 i 17-) ~ ilsb for dash52i l..j 'wff$ 1 lilt 15 ---] $$---, vj1ij7jj ilsil for 0.0.511531__- l wqm notes ~ ,. output data va"d. . 2, if sih cont...1 and trll19ar 8<. ""d tagathr, pul... width must be 4".10.0.51152)15"0 (nasu531 m!n to allow the sih amplifier to acquire the input signal, ii the adc is only used, the t,11ige, pulse must be 100n. min. figure 3. da$1152/da$1153 timing diagram -3- -~-~ aaalogvoltage connel:t connect connect input vinor s/h out analog common ref out range to to to oto +:5v ana in i, anainz, ground nc* anain3 oto + iov anain2 ground nc* anain 3 ana in 1 :!:5v ana in 1 ground, ana in 2 ana in 3 :!:jov ana in 3 ground, anain2 anajn 1 obsolete
analog devices fax-on-demand hotline - page 5 das1152/das1153 gain and offset adjustment the das1l52/das1l53 contain internal gain and offset adjustment potentiometers. each potentiometer has ample adjustment range so that gain and offset errors can be trimmed to zero. since offset calibration is not affected by changes in gain calibration, it should be performed prior to gain calibration. proper gain and offset calibration requires great care and the use of extremely sensitive and accurate reference instruments. the voltage standard used as a signal source must be very stable and be capable of being set to within :t l/iolsb of the desired value at any point within its range. offset calibration for a 0 to + 10v unipolar range set the input voltage precisely to + 305j.1.v for the das1l52 and + 1 53j.1.v for the dasli53. for a 0 to +5v unipolar range set the input to + 153j.lv for the das1l52 and + 16j.1.v for the das1l53. then adjust the zero potentiometer until the converter is just on the verge of switching from 000 000 to 000 '001. for the :t sv bipolar range set the input voltage precisely to +305j.1.v for the das1l52 and + 153j.1.v for the das1i53. for a :t iov bipolar range set the input voltage precisely to + 61oj.i. v for the das1152 and +30sj.l.v for tbe das1153. adjust the zero potentiometer until the offset binary coded units arc just on the verge of switching from 000 000 to 000 001 and the two's complement coded w1its are just on the verge of switching from 100 000 to 100 001. gain calibration set the input voltage precisely to +9.99909v (daslls2)1 + 9. 99954v (das1i53) for tbe 0 to + 10v units, +4.99954v (das1l52)/+4.99971v (das1l53) for 0 to +sv units, +9.99817v (daslls2)/+9.99909v (das1l53) for :t jov units, or +4.99909v (daslls2)/+4.99954v (das1l53) for :t 5v w1its. note that these values are i 1/2lsbs less tban nominal full scale. adjust the gain potentiometer until binary and offset binary coded units are just on the verge of switching from 11 10 to 11 11 and two's complement coded units are just on the verge of switching from 011 10 to 011 .11. das1152/das1l53 inputioutput relationships the das1152/das1153 produces a true binary coded output when configured as a unipolar device. configured as a bipolar device, it can produce either offset binary or two's complement output codes. the most significant bit (msb) is used to obtain the binary and offset binary codes while (msb) is used to obtain two's complement coding. table ii shows the das 1 i 52/das 1153 unipolar analog input/digital output relationships. tables iii and iv show the das1l52/daslls3 bipolar analog input/digital output relationships. nominal bipolar input .output relationships table ii. unipolar input/output relationships analog input 010 +10 dashs2 +9,99939v + ;,oooov + !.25000v +0.0006v +o.oooov dto + sv range: dasus2 dashs3 +4.99969v +4.99984v +2.50000v +2.50000y +0.62500v +o.62500v +o.0003v +o.00015v +o.oooov +o.ooooy ange dashs3 +9.9996!n + 5.00000y + !.25000y +o.0003v +o.oooov qjgit al output binary code dash53 111111111111111 1 00 000 000 000 000 00 1 000 000 000 000 000 000 000 000 00 1 000 000 000 000 000 daslls2 11111111111111 10 000 000 000 000 00 1 00 000 000 000 00 000 000 000 00 i 00 000 000 000 000 table /ii. das1152 bipolar input/ou~put relationships analog input :t:svrange z 10v range + 4. 99939v +9.99878v + 2.50000y + 5.0000y +0.0006iy +0.ooi22y +o.ooooov +o.ooooov - 5.00000y - 10.00000y digital output offset binary code two's complemcot code 11111111111111 01111111111111 ii 000 000 000 000 01 000 000 000 000 10000000 000 001 00 000 000 000 001 i 0 000 000 000 000 00 000 000 000 000 00 000 000 000 000 i 0 000 000 000 000 table iv. das1153 bipolar input/output relationships aiialoe input : sv range :!:10v range +4.99969v +9.99939v +2.50000v +5.0000y +o.0003v + 0.0006 iv +o.ooooov +o.oooooy - 5.00000v - io.ooooov digital output ollsetblnarycode two'. complement code iii iii 111 111 111 011 iii 111 iii iii 11 0 000 000 000 000 0 1 0 000 000 000 000 1 00 000 000 000 00 i 000 000 000 000 00 1 1 00 000 000 000 000 000 000 000 000 000 000 000 000 000 000 i 00 000 000 000 000 tri-state digital output the adc digital outputs are provided in parallel format to the output tri-state buffers. the output information can be applied to a data bus in either a one-byte or a two-byte format by using the high byte enable and low byte enable terminals. if the tri-state feature is not required, normal digital outputs can be obtained by connecting the enable pins to ground. power supply and grounding connections although the analog power ground and the digital ground are connected in the das 1152/das i 153, care must still be taken to provide proper grounding due to the high accuracy nature of these devices. though only general guidelines can be given, grounding should be arranged in such a manner as to avoid ground loops and to minimize the coupling of voltage drops (on the high current carrying logic supply ground) to the sensitive analog circuit sections. analog and digital grow1ds should remain separated on the pc board and terminated at the respective dasi152/das 1153 terminals. no power supply decoupling is required since, the das1152/ das1l53, contain high quality tantalum capacitors on each of the power supply inputs to ground. -4- rev. 'a - -~ obsolete
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